DocumentCode :
1496837
Title :
Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule
Author :
Ibe, Eishi ; Taniguchi, Hitoshi ; Yahagi, Yasuo ; Shimbo, Ken-ichi ; Toba, Tadanobu
Author_Institution :
Production Eng. Res. Lab., Hitachi, Ltd., Yokohama, Japan
Volume :
57
Issue :
7
fYear :
2010
fDate :
7/1/2010 12:00:00 AM
Firstpage :
1527
Lastpage :
1538
Abstract :
Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.
Keywords :
Monte Carlo methods; SRAM chips; integrated circuit design; CORIMS; CYRIC; LANSCE; Monte-Carlo simulator; SRAM; TSL; design rule; neutron fields; neutron-induced soft error; terrestrial neutron-induced soft-error; Electrical safety; Error correction codes; Identity-based encryption; Life estimation; Neutrons; Predictive models; Protection; Redundancy; Single event upset; Testing; Bit multiplicity; cosmic ray impact simulator (CORIMS); multi-cell upset (MCU); multi-node upset (MNU); scaling; single event upset (SEU); static random access memories (SRAMs);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2010.2047907
Filename :
5467170
Link To Document :
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