DocumentCode
1496909
Title
2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique
Author
Kishine, Keiji ; Takiguchi, K. ; Ichino, H.
Author_Institution
NTT Opt. Network Syst. Labs., Kanagawa
Volume
35
Issue
5
fYear
1999
fDate
3/4/1999 12:00:00 AM
Firstpage
360
Lastpage
361
Abstract
A 2.5 Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabricated using 0.5 μm Si bipolar technology. This CDR IC operates more stably in that it can tolerate greater variations in temperature and supply voltage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations
Keywords
bipolar integrated circuits; circuit stability; digital communication; elemental semiconductors; mixed analogue-digital integrated circuits; optical communication equipment; phase locked loops; silicon; synchronisation; timing circuits; timing jitter; very high speed integrated circuits; 0.5 micron; 2.5 Gbit/s; ITU-T recommendations; Si; Si bipolar technology; clock recovery circuit IC; data recovery circuit IC; duplicated PLL technique; jitter characteristics specifications; monolithic IC; optical transmission systems; phase-locked loop technique; stable operation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19990294
Filename
757115
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