Title :
Self-checking synchronous controller design
Author :
Kia, S.M. ; Parameswaran, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Queensland Univ., St. Lucia, Qld., Australia
fDate :
1/1/1999 12:00:00 AM
Abstract :
Efficient models are introduced for totally self-checking/code disjoint (TSC/CD) and strongly fault-secure/strongly code disjoint (SFS/SCD) synchronous controller models. These models are based on two low-cost, modular, TSC edge-triggered and error-propagating CD flip-flops. Properties of the proposed synchronous controller models are proven. The design procedure for these models and their proper applications are explained
Keywords :
built-in self test; flip-flops; logic testing; TSC edge-triggered; code disjoint; controller models; flip-flops; synchronous controller; totally self-checking;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:1990243
