DocumentCode
1497425
Title
Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally spaced polynomials
Author
Lee, Chiou-Yng ; Lu, Erl-Huei ; Lee, Jau-Yien
Author_Institution
Dept. of Electr. Eng., Chang Gung Univ., Tao-Yuan, Taiwan
Volume
50
Issue
5
fYear
2001
fDate
5/1/2001 12:00:00 AM
Firstpage
385
Lastpage
393
Abstract
Two operations, the cyclic shifting and the inner product, are defined by the properties of irreducible all one polynomials. An effective algorithm is proposed for computing multiplications over a class of fields GF(2m) using the two operations. Then, two low-complexity bit-parallel systolic multipliers are presented based on the algorithm. The first multiplier is composed of (m+1)2 identical cells, each consisting of one 2-input AND gate, one 2-input XOR gate, and three 1-bit latches. The other multiplier comprises of (m+1)2 identical cells and mXOR gates. Each cell consists of one 2-input AND gate, one 2-input XOR gate, and four 1-bit latches. Each multiplier exhibits very low latency and propagation delay and is thus very fast. Moreover, the architectures of the two multipliers can be applied in computing multiplications over the class of fields GF(2m ) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m
Keywords
digital arithmetic; flip-flops; multiplying circuits; polynomials; systolic arrays; 1-bit latches; 2-input AND gate; 2-input XOR gate; GF(2m) fields; XOR gate; bit-parallel systolic multipliers; cyclic shifting; inner product; irreducible all one polynomials; mXOR gates; polynomials; propagation delay; Arithmetic; Circuits; Computer architecture; Cryptography; Electrostatic precipitators; Error correction; Galois fields; Latches; Polynomials; Propagation delay;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.926154
Filename
926154
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