Title :
Low-jitter phase-locked loop based on pseudo-differential delay elements
Author :
Park, Sungkyung ; Choi, Youngdon ; Lee, Sang-Geun ; Jung, Yeon-Jae ; Park, Sin-Chong ; Kim, Wonchan
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
5/24/2001 12:00:00 AM
Abstract :
A phase-locked loop (PLL) that is highly robust to supply/substrate noise is described. A new type of voltage-controlled oscillator (VCO) based on pseudo-differential delay elements is presented. The proposed circuit is implemented using a 0.35 μm CMOS process technology with a 3.3 V supply. It generates 16 clock phases at 250 MHz, tailored to gigabit link applications
Keywords :
CMOS integrated circuits; delay circuits; high-speed integrated circuits; integrated circuit noise; jitter; phase locked loops; voltage-controlled oscillators; 0.35 micron; 250 MHz; 3.3 V; CMOS process technology; VCO; gigabit link applications; low-jitter PLL; phase-locked loop; pseudo-differential delay elements; substrate noise robustness; supply noise robustness; voltage-controlled oscillator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010460
