eIRA LDPC Codes on FPGA

eIRA codes are iteratively decodable low-density parity-check (LDPC) codes. They not only offer superior performance to alternative approaches, but they allow linear-time encoding. Well-designed eIRA codes also achieve extremely low error-rate floors. In this letter, we successfully implement a common FPGA platform for eIRA codes. As a demonstration, we took an example parity-check matrix from Example 4 in . For a maximum of seven iterations and 7 bits precision, the error-rate degradation is less than two tenths of a decibel compared to the double precision floating point result. It is important to note that there is no error rate floor close to BER of 10^-12. Such a performance is often requested in practical applications, but has never been achieved by graphic codes in the literature so far as we know.