Title :
Hidden double data transfer scheme for MDL design [merged DRAM logic]
Author :
Park, Se-Jeong ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
5/24/2001 12:00:00 AM
Abstract :
A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 μm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory
Keywords :
DRAM chips; cache storage; integrated logic circuits; 0.16 micron; L2 cache memory; general design framework; hidden double data transfer scheme; high-speed DRAM data transfer scheme; logically divided DRAM row address mapping; merged DRAM logic designs; read access; write access;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010489
