• DocumentCode
    1499070
  • Title

    Incremental switch-level analysis

  • Author

    Beatty, D.L. ; Bryant, Randal E.

  • Author_Institution
    Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
  • Volume
    5
  • Issue
    6
  • fYear
    1988
  • Firstpage
    33
  • Lastpage
    42
  • Abstract
    An algorithm is presented for extracting a two-level subnetwork hierarchy from flat netlists. They discuss the application of this algorithm to incremental circuit analysis in the Cosmos compiled switch-level simulator. The algorithm decreases the network preprocessing time for Cosmos by nearly an order of magnitude. The file system is used as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy-extraction algorithm computes a hash signature for each subnetwork by coloring vertices somewhat the way wirelist-comparison programs do. It then identifies duplicates, using standard hash-table techniques.<>
  • Keywords
    circuit layout CAD; file organisation; Cosmos compiled switch-level simulator; coloring vertices; file system; flat netlists; hash table; hierarchy-extraction algorithm; incremental switch-level synthesis; Analytical models; Circuit analysis; Circuit simulation; Computational modeling; File systems; Hardware; Information analysis; MOSFETs; Switches; Switching circuits;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.9270
  • Filename
    9270