Title :
Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications
Author :
Lin, Lang ; Srivathsa, Sudheendra ; Krishnappa, Dilip Kumar ; Shabadi, Prasad ; Burleson, Wayne
Author_Institution :
Intel Corp., Hudson, MA, USA
Abstract :
Harnessing unique physical properties of integrated circuits to enhance hardware security and IP protection has been extensively explored in recent years. Physical unclonable functions (PUFs) can sense inherent manufacturing variations as chip identifications. To enable the integration of PUFs into low-power and security applications, we study the impacts of process technology and supply voltage scaling on arbiter-based PUF circuit design. A Monte Carlo-based statistical analysis has demonstrated that advanced technologies and reduced supply voltage can improve the PUF uniqueness due to increased delay sensitivity. A linear regression approach has been leveraged to generate PUF delay profile by factoring in device, supply voltage and temperature variations. An accurate SVM-based software modeling analysis is used to verify the PUF additive delay behavior. Finally, postsilicon validation on arbiter-based PUF test chips in 45 nm SOICMOS technology has been correlated to simulation results and the inconsistency has been discussed. The test chips can resist the basic support vector machine attack due to the dynamic circuit effects and the limitation of our delay model.
Keywords :
CMOS integrated circuits; Monte Carlo methods; delays; electronic engineering computing; integrated circuit design; integrated circuit testing; low-power electronics; power aware computing; regression analysis; silicon; silicon-on-insulator; statistical analysis; support vector machines; IP protection; Monte Carlo-based statistical analysis; PUF additive delay behavior; SOI CMOS technology; SVM-based software modeling analysis; Si; arbiter-based PUF circuit design; chip identification; delay sensitivity; dynamic circuit effect; hardware security enhancement; integrated circuit property; linear regression approach; low-power security application; manufacturing variation; physical unclonable function; post silicon validation; size 45 nm; supply voltage scaling; support vector machine; Delay; Integrated circuit modeling; Materials; Noise measurement; Reliability; Security; Vectors; Physical unclonable functions; statistical simulation; subthreshold circuits; support vector machine (SVM) modeling attack;
Journal_Title :
Information Forensics and Security, IEEE Transactions on
DOI :
10.1109/TIFS.2012.2195174
