Power-area-efficient transient-improved capacitor-free FVF-LDO with digital detecting technique

Author

Jianping Guo ; Ho, Mantak ; Ka Yee Kwong ; Ka Nang Leung

Author_Institution

Sch. of Phys. & Eng., Sun Yat-sen Univ., Guangzhou, China

Volume

51

Issue

1

fYear

2015

fDate

1 8 2015

Firstpage

94

Lastpage

96

Abstract

A fast-transient capacitor-free low-dropout regulator (LDO) based on a flipped-voltage-follower (FVF) structure has been designed with the proposed digital detecting technique. By increasing the slewing at the gate of the power transistor through detecting the dynamic changes inside the circuit, load-transient recovery time can be decreased by 99.8%. The quiescent current of the proposed LDO is only 3.9 μA under normal operation. In addition, the circuit maintains a small chip area of 0.04 mm² under 0.18 μm CMOS technology since no large RC components are needed to couple the output voltage spikes.

Keywords

CMOS analogue integrated circuits; operational amplifiers; transient analysis; voltage regulators; CMOS technology; DDT; current 3.9 muA; digital detecting technique; flipped-voltage-follower structure; load-transient recovery time; low-dropout regulator; output voltage spikes; power transistor; power-area-efficient transient-improved capacitor-free FVF-LDO; size 0.18 mum;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2014.3330

Filename

7006841