Power-area-efficient transient-improved capacitor-free FVF-LDO with digital detecting technique

A fast-transient capacitor-free low-dropout regulator (LDO) based on a flipped-voltage-follower (FVF) structure has been designed with the proposed digital detecting technique. By increasing the slewing at the gate of the power transistor through detecting the dynamic changes inside the circuit, load-transient recovery time can be decreased by 99.8%. The quiescent current of the proposed LDO is only 3.9 μA under normal operation. In addition, the circuit maintains a small chip area of 0.04 mm² under 0.18 μm CMOS technology since no large RC components are needed to couple the output voltage spikes.