DocumentCode :
1499345
Title :
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement
Author :
Lee, Kuen-Jong ; Hsieh, Tong-Yu ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume :
31
Issue :
5
fYear :
2012
fDate :
5/1/2012 12:00:00 AM
Firstpage :
754
Lastpage :
764
Abstract :
Acceptable faults in a circuit under test (CUT) refer to those faults that have no or only minor impacts on the performance of the CUT. A circuit with an acceptable fault may be marketable for some specific applications. Therefore, by carefully dealing with these faults during testing, significant yield improvement can be achieved. Previous studies have shown that the patterns generated by a conventional automatic test pattern generation procedure to detect all unacceptable faults also detect many acceptable ones, resulting in a severe loss on achievable yield improvement. In this paper, we present a novel test methodology called multiple test set detection (MTSD) to totally eliminate this overdetection problem. A basic test set generation method is first presented, which depicts a fundamental scheme to generate appropriate test sets for MTSD. We then describe an enhanced test generation method that can significantly reduce the total number of test patterns. Solid theoretical derivations are provided to validate the effectiveness of the proposed methods. Experimental results show that in general an 80%-99% reduction in the number of test patterns can be achieved compared with previous work addressing this problem.
Keywords :
automatic test pattern generation; integrated circuit testing; integrated circuit yield; acceptable faults; automatic test pattern generation procedure; circuit under test; multiple test set detection; overdetection elimination; test set generation method; yield improvement; Automatic test pattern generation; Circuit faults; Degradation; Educational institutions; Electrical engineering; Error analysis; Integrated circuit modeling; Acceptable fault; error rate; error-tolerance; overdetection; performance degradation; yield improvement;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2011.2179036
Filename :
6186858
Link To Document :
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