• DocumentCode
    1499688
  • Title

    Resynthesis and retiming for optimum partial scan

  • Author

    Chakradhar, Srimat T. ; Dey, Sujit

  • Author_Institution
    NEC Res. Inst., Princeton, NJ, USA
  • Volume
    18
  • Issue
    5
  • fYear
    1999
  • fDate
    5/1/1999 12:00:00 AM
  • Firstpage
    621
  • Lastpage
    630
  • Abstract
    An effective partial scan approach selects flip-flops (FPs) in the minimum feedback vertex set (MFVS) of the FF dependency graph, so that all loops, except self-loops, are broken. However, the MFVS of the circuit (the minimum number of gates whose removal makes the circuit acyclic) is a lower bound and in many cases, significantly smaller than the MFVS of the FF dependency graph. Since only FFs can be considered for scan, this paper investigates the possibility of repositioning FFs so that, in the modified circuit, every circuit MFVS gate drives at least one FF that can be scanned. We show that resynthesis and retiming can always transform any circuit into an equivalent circuit whose FF dependency graph MFVS is equal to the MFVS of the original circuit. Therefore, the MVFS of a circuit is a tight lower bound on the number of scan FFs needed. We first identify the necessary and sufficient conditions under which legal retiming can produce the desired FF repositioning. We show that circuits that do not satisfy these conditions can always be suitably modified using two new resynthesis transformations. The modified circuit can always be retimed to achieve the desired FF repositioning. Experimental results for several large sequential benchmarks show that the number of scan FFs required for the resynthesized and retimed circuit is significantly smaller than that required for the original circuit
  • Keywords
    circuit feedback; design for testability; equivalent circuits; flip-flops; graph theory; logic design; logic testing; timing; cycle breaking; dependency graph; digital testing; equivalent circuit; flip-flop; minimum feedback vertex set; optimum partial scan; resynthesis; retiming; Automatic test pattern generation; Circuit faults; Circuit testing; Equivalent circuits; Feedback loop; Flip-flops; National electric code; Sequential analysis; Sequential circuits; Sufficient conditions;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.759078
  • Filename
    759078