A parallel embedded-processor architecture for ATM reassembly

Author

Hobson, Richard F. ; Wong, P.S.

Author_Institution

Sch. of Comput. & Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada

Volume

7

Issue

1

fYear

1999

fDate

2/1/1999 12:00:00 AM

Firstpage

23

Lastpage

37

Abstract

The asynchronous transfer mode (ATM) reassembly algorithm for adaptation layer five is broken down into concurrent tasks for efficient VLSI implementation. VHDL and HSPICE simulations show that the proposed reassembly chip architecture will function with ATM line rates up to 700 Mb/s. The architecture is based upon three embedded lightweight processors, a variety of supporting circuitry, and a peripheral component interface (PCI) bus host interface. An important architectural feature is the use of a paged memory management system for the reconstruction of variable length messages

Keywords

VLSI; asynchronous transfer mode; circuit simulation; digital signal processing chips; embedded systems; hardware description languages; paged storage; parallel architectures; peripheral interfaces; storage management; system buses; 700 Mbit/s; ATM line rates; ATM reassembly algorithm; HSPICE simulation; VHDL simulation; VLSI implementation; adaptation layer five; asynchronous transfer mode; bus host interface; concurrent tasks; paged memory management system; parallel embedded-processor architecture; peripheral component interface; reassembly chip architecture; variable length messages reconstruction; Application software; Asynchronous transfer mode; B-ISDN; Bandwidth; Buffer storage; Hardware; Media Access Protocol; Memory management; Network interfaces; Workstations;

fLanguage

English

Journal_Title

Networking, IEEE/ACM Transactions on

Publisher

ieee

ISSN

1063-6692

Type

jour

DOI

10.1109/90.759314

Filename

759314