Title :
A 2- mu m BiCMOS process utilizing selective epitaxy
Author :
O, Kenneth K. ; Lee, Hae-Seung ; Reif, R. ; Frank, W.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
A 2- mu m BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2- mu m CMOS process with a poly-to-n/sup +/ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors.
Keywords :
BIMOS integrated circuits; epitaxial growth; integrated circuit technology; semiconductor growth; 10 V; 2 micron; 5 GHz; BiCMOS process; analog/digital applications; cutoff frequency; masking steps; monolithic IC fabrication; nonoptimized vertical p-n-p structure; poly-to-n/sup +/ capacitors; selective epitaxial growth; vertical n-p-n bipolar structure; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Capacitors; Epitaxial growth; Epitaxial layers; Etching; MOSFETs; Strips;
Journal_Title :
Electron Device Letters, IEEE
