Single Cycle Access Structure for Logic Test

This paper proposes a new single cycle access test structure for logic test. It eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles. This leads to more realistic circuit behavior during stuck-at and at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycles per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. Results are compared to other published solutions on ISCAS´89 netlists. The structure allows an additional on-chip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self test (BIST) and massive parallel scan chains.