A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit

Author

Wang, Chua-Chin ; Hsu, Chia-Hao ; Liao, Szu-Chia ; Liu, Yi-Cheng

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

19

Issue

8

fYear

2011

Firstpage

1481

Lastpage

1485

Abstract

A fully bidirectional mixed-voltage input/output (I/O) buffer using a novel floating N-well circuit is presented. To provide appropriate gate voltages for output stage transistors, a dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon using 0.18 μm CMOS process that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.

Keywords

CMOS logic circuits; buffer circuits; leakage currents; CMOS process; PAD voltage detector; bidirectional mixed-voltage input/output buffer; dynamic gate bias generator; gate-tracking circuit; leakage current; novel floating N-well circuit; output stage transistors; wide voltage range digital I/O design; Atherosclerosis; Circuits; Degradation; Detectors; Hot carriers; Leak detection; Leakage current; Logic; Silicon; Voltage; Dynamic gate bias; floating N-well; mixed-voltage; wide-range input/output (I/O) buffer;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2010.2049668

Filename

5471068