Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (V_t1) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (C_ESD) of 150 fF and prompt response to very fast ESD pulses with rising time (t_r) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of ~7 V/μ m².