Abstract :
The author reports on the theory and practice behind an innovative 32 bit RISC processor core, whose architecture can be customised to provide the optimum design solution for processor-based application-specific integrated circuits. In its basic configuration, the ARC processor, the Tangent-A4, is a four-stage pipeline device, with instructions, data and address formats all 32 bit. It also boasts separate instruction and data buses (Harvard architecture), data and instruction caches, and a unique host interface (parallel, JTAG or user defined), giving external devices access to the internal registers and memory
Keywords :
application specific integrated circuits; microprocessor chips; pipeline processing; reduced instruction set computing; 32 bit; ARC processor; Harvard architecture; RISC processor core; Tangent-A4; application-specific integrated circuits; data bus; data cache; four-stage pipeline device; host interface; instruction bus; instruction cache; optimum design; processor architecture; processor-based ASIC; registers;
