Bias optimization for switched capacitor amplifiers

Author

Opris, Ion E. ; Lewicki, Laurence D.

Author_Institution

Data Acquisition Products, Nat. Semicond. Corp., Santa Clara, CA, USA

Volume

44

Issue

12

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

985

Lastpage

989

Abstract

Bias optimization is one of the most important design issues in many low power applications. Several biasing schemes for switched capacitor applications are analyzed in this paper from the settling time point of view. A bias circuit is described that provides the best tradeoff between the slew-rate and the unity gain bandwidth of a single dominant-pole opamp over process and temperature variations. Theoretical analysis and simulations confirm a quasi-constant settling time with minimal process dependence

Keywords

circuit optimisation; operational amplifiers; switched capacitor networks; bias optimization; design; low power circuit; process dependence; settling time; simulation; single dominant-pole opamp; slew rate; switched capacitor amplifier; temperature variation; unity gain bandwidth; Analytical models; Bandwidth; Circuit simulation; Design optimization; High power amplifiers; Performance analysis; Switched capacitor circuits; Temperature dependence; Transconductance; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.644533

Filename

644533