Title :
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
Author :
Abo, Andrew M. ; Gray, Paul R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
5/1/1999 12:00:00 AM
Abstract :
A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 μm CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; integrated circuit reliability; low-power electronics; pipeline processing; 0.6 micron; 1.5 V; 10 bit; 36 mW; CMOS; MOS switches; bootstrapping technique; device reliability constraints; least significant bit; maximum differential nonlinearity; maximum integral nonlinearity; peak signal-to-noise-and-distortion ratio; pipeline analog-to-digital converter; power consumption; terminal voltages; Analog-digital conversion; CMOS technology; Clocks; Computer architecture; Integrated circuit reliability; Integrated circuit technology; Low voltage; Operational amplifiers; Pipelines; Switches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
