A portable digital DLL for high-speed CMOS interface circuits

Author

Garlepp, Bruno W. ; Donnelly, Kevin S. ; Kim, Jun ; Chau, Pak S. ; Zerbe, Jared L. ; Huang, Charles ; Tran, Chanh V. ; Portmann, Clemenz L. ; Stark, Donald ; Chan, Yiu-Fai ; Lee, Thomas H. ; Horowitz, Mark A.

Author_Institution

Rambus Inc., Mountain View, CA, USA

Volume

34

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

632

Lastpage

644

Abstract

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-μm standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm²

Keywords

CMOS digital integrated circuits; delay lock loops; high-speed integrated circuits; phase control; synchronisation; timing jitter; 0.4 micron; 1.7 to 3.3 V; 400 MHz; 60 mW; digital delay-locked loop; dual delay lines; duty cycle correcting multiplexers; end-of-cycle detector; high-speed CMOS interface circuits; jitter performance; phase blenders; portable digital DLL; standard CMOS process; Associate members; CMOS digital integrated circuits; CMOS process; Circuit testing; Clocks; Delay lines; Jitter; Phase detection; Standards development; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.760373

Filename

760373