A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface

Author

Kim, C. ; Kyung, K.-H. ; Jeong, W.-P. ; Kim, J.S. ; Moon, B.-S. ; Chai, J.-W. ; Yim, S.-M. ; Choi, J.-H. ; Han, K.-H. ; Park, C.J. ; Hwang, H.-S. ; Choi, H. ; Cho, S.-B. ; Portmann, Clemenz L. ; Cho, S.I.

Author_Institution

Samsung Electron. Co. Ltd., Yongin City, South Korea

Volume

34

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

645

Lastpage

652

Abstract

A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using (1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, (2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and (3) a flexible column redundancy scheme to efficiently increase redundancy coverage using a shifted I/O line scheme for multibank architecture

Keywords

CMOS memory circuits; DRAM chips; delay lock loops; low-power electronics; memory architecture; memory protocols; redundancy; 2 GByte/s; 2.5 V; 72 Mbit; DLL circuit; delay-locked-loop; flexible column redundancy scheme; high-speed differential clock; multibank architecture; packet protocol; packet-based DRAM; power noise reduction; prefetch architecture; rotated hierarchical I/O architecture; shifted I/O line scheme; Access protocols; Bandwidth; Circuit noise; Clocks; Delay lines; Flexible printed circuits; Moon; Noise reduction; Prefetching; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.760374

Filename

760374