A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

Author

Sato, Takashi ; Nishio, Yoji ; Sugano, Toshio ; Nakagome, Yoshinobu

Author_Institution

Semicond. Technol. Dev. Div., Hitachi Ltd., Tokyo, Japan

Volume

34

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

653

Lastpage

660

Abstract

This paper describes a 5-GByte/s data-transfer scheme suitable for synchronous DRAM memory. To achieve a higher data-transfer frequency, the properties were improved based on the frequency analysis of the memory system. Then, a bit-to-bit skew compensation technique that eliminates incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by controlling transmission timing of every data bit. Simulated maximum data-transfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/365 MHz, ×64 bit, double data rate) for data write/read operation, respectively

Keywords

DRAM chips; VLSI; delay circuits; timing; 321 to 365 MHz; 5.1 to 5.8 GByte/s; bit-to-bit skew control; data write/read operation; data-transfer scheme; frequency analysis; multioutput controlled delay circuit; synchronous DRAM; transmission timing; Bandwidth; Circuit simulation; Control systems; Delay; Electric variables; Frequency; Integrated circuit technology; Microprocessors; Read-write memory; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.760375

Filename

760375