A 5.3-GB/s embedded SDRAM core with slight-boost scheme

Author

Yamazaki, Akira ; Yamagata, Tadato ; Hatakenaka, Makoto ; Miyanishi, Atsushi ; Hayashi, Isao ; Tomishima, Shigeki ; Mangyo, Atsuo ; Yukinari, Yoshio ; Tatsumi, Takashi ; Matsumura, Masashi ; Arimoto, Kazutami ; Yamada, Michihiro

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

34

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

661

Lastpage

669

Abstract

This paper describes a slight-boost scheme to improve a transistor performance in system large-scale integrated circuits, which integrate logic circuits and 1-Tr/1-C DRAMs. In this scheme, an embedded SDRAM core has been developed for graphic and multimedia applications. Its maximum operating frequency is 166 MHz, with a peak data rate of 5.3 GB/s. As well, a fast row-address access time of 22 ns has been achieved. The SDRAM core has been fabricated by means of a 0.3-μm quad-polysilicon, triple metal, triple-well CMOS process. This SDRAM core has a block write function, enhanced by a multiselect block write scheme, and a synchronous direct memory-access test circuit has been implemented to reduce the number of test pads

Keywords

CMOS memory circuits; DRAM chips; VLSI; embedded systems; integrated circuit testing; 0.3 micron; 166 MHz; 22 ns; 5.3 GB/s; block write function; embedded SDRAM core; maximum operating frequency; multimedia applications; multiselect block write scheme; peak data rate; quad-polysilicon; row-address access time; slight-boost scheme; synchronous direct memory-access test circuit; system large-scale integrated circuits; test pads; triple-well CMOS process; Circuit testing; Frequency; Graphics; Large scale integration; Logic circuits; Logic design; MOSFETs; Random access memory; SDRAM; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.760377

Filename

760377