A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors

Author

Klass, Fabian ; Amir, Chaim ; Das, Ashutosh ; Aingaran, Kathirgamar ; Truong, Cindy ; Wang, Richard ; Mehta, Anup ; Heald, Ray ; Yee, Gin

Author_Institution

Sun Microsyst. Inc., Palo Alto, CA, USA

Volume

34

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

712

Lastpage

716

Abstract

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well

Keywords

CMOS logic circuits; flip-flops; synchronisation; timing; clock load; delay penalty; dynamic flip-flops; edge-triggered flip-flops; embedded logic; high-performance processor application; latency; pipeline overhead reduction; semidynamic flip-flops; single-phase clock scheme; synchronization element; Circuits; Clocks; Delay; Flip-flops; Latches; Logic functions; Logic gates; Microprocessors; Pipeline processing; Synchronization;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.760383

Filename

760383