An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C_f^ext) of conventional T-shaped gate HJFET´s. By introducing a T-shaped SiO₂-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-μm gate-openings which were suitable for reducing the C_f^ext and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-μm DDS gate HJFETs are fabricated. The 0.1-μm n-Al _0.2Ga_0.8As/i-In_0.15Ga_0.85As pseudomorphic DDS gate HJFETs exhibited an excellent V_th standard-deviation (σV_th) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO₂ passivation film had very high performance with an f_T of 120 GHz and an f_max of 165 GHz, due to the low C_f^ext with the DDS gate structure. In addition, a high f_T of 151 GHz and an f_max of 186 GHz were obtained without a SiO₂ passivation film. This fabrication technology shows great promise for high-speed IC applications