A leakage current mechanism caused by the interaction of residual oxidation stress and high-energy ion implantation impact in advanced CMOS technology

Author

Lee, Hyeokjae ; Hwang, Jeong Mo ; Park, Young June ; Min, Hong Shick

Author_Institution

Dept. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

20

Issue

5

fYear

1999

fDate

5/1/1999 12:00:00 AM

Firstpage

251

Lastpage

253

Abstract

In this paper, we report abnormal junction leakage current characteristics in sub-quarter micron CMOS formed by OSELO-II isolation method and high-energy ion implantation for well formation. The phenomena have not been found in other isolation schemes such as single Si/sub 3/N/sub 4/ spacer OSELO (SSS-OSELO), modified conventional LOCOS (MLOCOS) and shallow trench isolation (STI). From the defect analysis and process simulation based on the actual recipe, the abnormal leakage is found to be generated from the lattice defects at the edge of field oxide and caused by the combination of oxidation stress, and high-energy ion implantation. A process condition in the high-energy ion implantation and isolation process is proposed to reduce the leakage current.

Keywords

CMOS integrated circuits; internal stresses; ion implantation; isolation technology; leakage currents; oxidation; semiconductor process modelling; OSELO-II isolation method; Si/sub 3/N/sub 4/; advanced CMOS technology; defect analysis; field oxide; high-energy ion implantation; high-energy ion implantation impact; lattice defects; leakage current mechanism; process simulation; residual oxidation stress; sub-quarter micron CMOS; well formation; Analytical models; CMOS process; CMOS technology; Ion implantation; Isolation technology; Laboratories; Lattices; Leakage current; Oxidation; Residual stresses;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.761030

Filename

761030