DocumentCode :
1501975
Title :
Low Hardware Complexity Pipelined Rank Filter
Author :
Prokin, Dragana ; Prokin, Milan
Author_Institution :
Higher Sch. of Electr. Eng. & Comput. Sci., Univ. of Belgrade, Belgrade, Serbia
Volume :
57
Issue :
6
fYear :
2010
fDate :
6/1/2010 12:00:00 AM
Firstpage :
446
Lastpage :
450
Abstract :
The major benefit of a disclosed low-hardware-complexity pipelined rank filter is reduction in hardware complexity and increase in processing speed, due to identical pipelined stages and the absence of mask bits. Field-programmable-gate-array realization of this filter significantly reduces the number of used logic elements and registers, in comparison with the best prior art methods, and, at the same time, increases the maximum operating frequency. One rank-sample result is available at the output on each clock cycle, thus enabling real-time nonlinear image processing.
Keywords :
computational complexity; field programmable gate arrays; nonlinear filters; field-programmable-gate-array realization; logic elements; logic registers; low hardware complexity; pipelined rank filter; real-time nonlinear image processing; Median filters; nonlinear filters; pipeline processing; rank filters; very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2010.2048371
Filename :
5471228
Link To Document :
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