48 cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding

This study presents a high-throughput deblocking filter accelerator with 48 cycles-per-macro-block processing capability for H.264. This innovation is achieved by considering both luminance data and chrominance data at the same time in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously compute filtering of four edges. Besides, interleaved memory organisation is adopted to eliminate all the data conflicts. This design keeps the data scanning order compliant with that recommended for data communication between modules in H.264 systems. Hence, no interfacing overhead is required for reordering the input and output data. After being implemented by using a 0.18-??m CMOS technology, this work can achieve the real-time performance requirement of 6 K (6000 ?? 4000@30 fps) application when operated at 135 MHz frequency at a cost of 41.6 K gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also possesses higher hardware computing efficiency.