Deembedding Accuracy for Device Scale and Interconnection Line Parasitics

Author

Lee, Jaeho ; Lee, Jaehong ; Jeon, Jongwook ; Jhon, Hee Sauk ; Shin, Hyungcheol

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea

Volume

19

Issue

11

fYear

2009

Firstpage

713

Lastpage

715

Abstract

In this letter, we investigate the deembedding accuracy of open-short (OS) and pad-open-short (POS) deembedding for transistor measurement and modeling. It is found that all of the transistor intrinsic element values except for the gate-resistance, Rg , are independent of the deembedding procedure. Furthermore, the difference in Rg is dependent on the device size. To analyze the origin of the deembedding difference, the equivalent circuits of the PADs and interconnection lines are constructed from the measured data by varying the values of parasitic parameters.

Keywords

CMOS integrated circuits; equivalent circuits; integrated circuit interconnections; transistors; deembedding accuracy; device scale parasitics; equivalent circuits; interconnection line parasitics; open-short deembedding; pad-open-short deembedding; transistor intrinsic element values; transistor measurement; $R_{g}$; Deembedding technique; RF CMOS; interconnection-line parasitics; open-short (OS); pad-open-short (POS);

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2009.2032011

Filename

5290042