Quantitative study of the impact of design and synthesis options on processor core performance

Author

Bautista, Tomas ; Nunez, Antonio

Author_Institution

SICAD Div., Univ. of Las Plamas de Gran Canaria, Spain

Volume

9

Issue

3

fYear

2001

fDate

6/1/2001 12:00:00 AM

Firstpage

461

Lastpage

473

Abstract

In this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies´ Epoch for obtaining the physical layout of the final circuits. These are mapped to 0.50- and 0.35-/spl mu/m, three metal layer processes in order to study the impact of VLSI scaling on SPARC microarchitectural features. The quantitative results obtained characterize suitable points in the design space. They show the extent to which microarchitecture, design, datapath granularity, and megacell decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL descriptions.

Keywords

VLSI; embedded systems; hardware description languages; integrated circuit design; integrated circuit modelling; logic design; microprocessor chips; 0.35 micron; 0.50 micron; Duet Technologies Epoch; SPARC v.8 Integer Unit; Synopsys; VHDL model; VLSI microarchitecture; circuit layout; datapath granularity; embedded processor core; hardware description language; logic synthesis; megacell operator; system-on-a-chip design; Circuit synthesis; Clocks; Design methodology; Design optimization; Instruction sets; Intellectual property; Microarchitecture; Space technology; System-on-a-chip; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.929580

Filename

929580