Capacitor voltage balancing of a five-level diode-clamped converter using minimum loss SVPWM algorithm for wide range modulation indices

This paper presents dc-link capacitor voltage balancing at any range of modulation indices utilizing the switching redundancies with minimum loss space vector pulse width modulation (MLSVPWM) algorithm. The five-level diode-clamped converter (DCC) is considered here. By deciding proper switching pattern and their duration jointly, the voltage across each capacitor can be controlled very competently. The MLSVPWM scheme generates all the available switching sequences, then based on capacitor voltages a five-level DCC can be mapped as any lower level DCC structure to increase available switching redundancy. Duty cycles are calculated for conventional two-level SVPWM and can be updated for any higher level converter structure by adding required level number. In the proposed scheme dc-capacitor voltage balancing is attained for high modulation indices in a simple and straightforward manner with minimal switching operation, without any requirement of complex calculations. The proposed MLSVPWM modulation technique for capacitor voltage balancing is verified using circuit simulations.