Title :
Differential pass-transistor clocked flipflop
Author :
Hwang, In-Chul ; Kang, Sung-Mo
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fDate :
6/7/2001 12:00:00 AM
Abstract :
A new differential pass-transistor clocked (DPTC) flipflop for low power application is presented. This design prevents speed degradation and redundant power consumption by cutting the low-impedance path of the struggling slave latch in the conventional pass-transistor clocked flipflop. Simulation results show that it reduces the power-delay product by 30% and the delay mismatch between two differential outputs to <2%
Keywords :
CMOS logic circuits; flip-flops; low-power electronics; timing; 0.35 micron; delay mismatch reduction; differential pass-transistor clocked flipflop; low power application; power-delay product reduction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010530
