Simulation of SSTL IO standard based power optimized parallel integrator design on FPGA

In this paper, we are implementing green Integrator. Digital integrator is an analog to digital converter. Which is designed in Xilinx ISE14.6 using various IO standard of SSTL in 28nm Kintex-7 FPGA. We are comparing different IO standard of SSTL to get minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. We are using different classes of SSTL in this entire paper and analyzed that when integrator device operating frequency is 1THz then there is 76.65% reduction in IO power of SSTL135_DCI as compare to SSTL135_R I/O Standard on Kintex-7 FPGA. Likewise at 2GHz, our integrator IO power reduction is 70.14% of SSTL12 with respect to SSTL12_DCI of IO standard using kintex-7 FPGA. When we see the dynamic clock power variations it´s almost same in every frequency i.e. 15%. Similarly when we operate parallel integrator at 200 GHz via kintex-7, there is 28.12% decrease in signal power of SSTL135_R with respect to SSTL135_DCI Standard. The Leakage power of integrator is decrease 16.21% of SSTL135_DCI as compared to SSTL135_R at 1 THz device operating frequency.