Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor

This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO power reduction of 79.49% for HSTL_I IO standard with Airtex-7 FPGA as compared to Virtex-6 FPGA. For HSTL_II_18, at 1THz, we are getting minimum IO power reduction of 5.90% with Virtex-6 FPGA as compared to Airtex-7 FPGA. For Airtex-7 FPGA, XC7A100T device, -3 speed grades, and CSG2324 package is used and For Virtex-6 FPGA, XC6VLX75T, -1 speed grade and FF484 package is used.