Accurate Machine-Learning-Based On-Chip Router Modeling

Author

Jeong, Kwangok ; Kahng, Andrew B. ; Lin, Bill ; Samadi, Kambiz

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California at San Diego, La Jolla, CA, USA

Volume

2

Issue

3

fYear

2010

Firstpage

62

Lastpage

66

Abstract

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average.

Keywords

learning (artificial intelligence); multiprocessing systems; network routing; network-on-chip; regression analysis; first-order design constraint; machine-learning-based regression techniques; multicore chips; networks-on-chip; on-chip router modeling; Delay estimation; Fabrics; Frequency estimation; Integrated circuit interconnections; Microarchitecture; Network-on-a-chip; Parametric statistics; Power system modeling; Textile industry; Timing; Machine learning; nonparemetric regression; on-chip networks;

fLanguage

English

Journal_Title

Embedded Systems Letters, IEEE

Publisher

ieee

ISSN

1943-0663

Type

jour

DOI

10.1109/LES.2010.2051413

Filename

5473105