Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices

Author

Cheng-Wei Luo ; Horng-Chih Lin ; Ko-Hui Lee ; Wei-Chen Chen ; Hsing-Hui Hsu ; Tiao-Yuan Huang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

58

Issue

7

fYear

2011

fDate

7/1/2011 12:00:00 AM

Firstpage

1879

Lastpage

1885

Abstract

Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.

Keywords

elemental semiconductors; nanostructured materials; nanowires; nitrogen compounds; silicon; silicon compounds; storage management chips; Si; SiO-NO-Si; block oxide-nitride interface; in situ deposition; nanocrystal location; nitride-tunnel oxide interface; silicon-oxide-nitride-oxide-silicon devices; trap-layer-engineered poly-Si nanowired gate-all-around SONOS memory devices; Electron traps; Logic gates; Programming; SONOS devices; Silicon; Surface treatment; Gate-all-around (GAA); nanocrystal (NC); nanowire (NW); poly-Si; silicon–oxide–nitride–oxide–silicon (SONOS);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2140321

Filename

5756229