Pseudo-FG technique for efficient energy harvesting

A novel 2.45 GHz RF power harvester has been implemented in a 90 nm standard CMOS process. The proposed architecture reduces the threshold voltage (Vth) by employing a pseudo floating-gate (pseudo-FG) new technique and achieves better performance compared with other conventional rectifiers at 90 nm and 2.45 GHz, without additional fabrication cost. The system is initially optimised via a matching-boosting circuit, which has a dominant dual role. Extremely low power ( 15.43 dBm) RF signals can be rectified and converted to 1.25 V DC.