HARTS: a distributed real-time architecture

Author

Shin, Kang G.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

24

Issue

5

fYear

1991

fDate

5/1/1991 12:00:00 AM

Firstpage

25

Lastpage

35

Abstract

The design, implementation, and evaluation of a distributed real-time architecture called HARTS (hexagonal architecture for real-time systems) are discussed, emphasizing its support of time-constrained, fault-tolerant communications and I/O (input/output) requirements. HARTS consists of shared-memory multiprocessor nodes, interconnected by a wrapped hexagonal mesh. This architecture is intended to meet three main requirements of real-time computing: high performance, high reliability, and extensive I/O. The high-level and low-level architecture is described. The evaluation of HARTS, using modeling and simulation with actual parameters derived from its implementation, is reported. Fault-tolerant routing, clock synchronization and the I/O architecture are examined.<>

Keywords

fault tolerant computing; parallel architectures; real-time systems; HARTS; I/O architecture; clock synchronization; fault tolerant routing; fault-tolerant communications; hexagonal architecture for real-time systems; hexagonal mesh; real-time architecture; shared-memory multiprocessor nodes; Aerospace industry; Automatic control; Computer architecture; Control systems; Hardware; Multiprocessor interconnection networks; Operating systems; Processor scheduling; Random access memory; Real time systems;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.76284

Filename

76284