Second harmonic current reduction and dynamic performance improvement in the two-stage inverters: An output impedance perspective

The instantaneous output power of the two-stage single-phase inverter pulsates at twice the output voltage frequency, resulting in the second harmonic current (SHC) in the front-end dc-dc converter. Although various control schemes can effectively reduce the SHC, they might make the front-end dc-dc converter suffer from poor dynamic performance. In this paper, a basic approach is proposed from the perspective of the output impedance to give considerations to both the SHC reduction and dynamic performance improvement, indicating that the output impedance of the front-end dc-dc converter should be designed relatively high at twice the output voltage frequency while relatively low at other frequencies. According to the proposed approach, one virtual impedance is introduced to be in series with the original output impedance while the other one is in parallel with the intermediate dc bus capacitor. Taking the buck-derived front-end dc-dc converter as an example, the implementation of the virtual impedance are presented, based on which, different control schemes in the previous publications can be synthesized. Finally, a 1-kVA prototype is fabricated in the lab and a comparative study is conducted on four different control schemes by both the theoretical analysis and experimental verification.