DocumentCode :
1505532
Title :
The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources
Author :
Chen, Phoebe Ping ; Ye, Andy
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
Volume :
19
Issue :
2
fYear :
2011
Firstpage :
283
Lastpage :
294
Abstract :
As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications. Large arithmetic intensive applications often contain a large proportion of datapath circuits. Since datapath circuits are designed to process multiple-bit-wide data, FPGAs implementing these circuits often have to transport a large amount of multiple-bit-wide signals from one computing element (such as a logic block, a DSP block, or a multi-bit addressable memory cell) to another. In this work, we investigate the area efficiency of FPGA routing resources for transporting multiple-bit-wide signals. It is shown that, for datapath circuits, the switch patterns used by the conventional routing architecture, which uniformly distribute routing switches across the routing tracks, are inefficient for connecting the computing elements to their tracks. The more efficient multi-bit aware patterns, which contain a densely populated single-bit region and a sparsely populated multi-bit region, can be effectively used to reduce the routing area of FPGAs for implementing arithmetic intensive applications by 6%-10%. It is also shown that the further sharing of configuration memory among the switches within the multi-bit aware patterns does not significantly increase their area efficiency since datapath circuits typically contain a mixture of multi-bit and single-bit signals-while configuration memory sharing can substantially increase the area efficiency of routing resources for transporting multi-bit signals, it also significantly reduces their ability for transporting single-bit signals. More importantly, configuration memory sharing can significantly reduce the effectiveness of the enhanced multi-bit aware patterns-patterns that incorporate both multi-bit aware and single-bit oriented switches within a single region in order to increase its ability for transporting both single-bit and multi-bit signals.
Keywords :
field programmable gate arrays; logic design; network routing; FPGA design; arithmetic-intensive applications; computing element; configuration memory sharing; conventional routing architecture; datapath circuits; distribute routing switches; field programmable gate array routing resources; logic capacity; multibit aware patterns; multibit correlation; multiple-bit-wide data; routing tracks; single-bit oriented switches; switch patterns; Area efficiency; datapath-oriented FPGA; field-programmable gate arrays (FPGAs); routing resources;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2029232
Filename :
5291700
Link To Document :
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