Title :
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking
Author :
Ghosh, Swaroop ; Mohapatra, Debabrata ; Karakonstantis, Georgios ; Roy, Kaushik
Author_Institution :
Logic Technol. Dev., Adv. Memory Design Group, Intel Inc., Portland, OR, USA
Abstract :
In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching.
Keywords :
clocks; power aware computing; adaptive clock stretching; adaptive clocking; clock frequency; high-yield ALU; logic optimization; occasional clock stretching; supply voltage scaling; voltage scalable high-speed robust hybrid arithmetic unit; voltage scalable robust ALU; Arithmetic; Clocks; Degradation; Delay; Energy consumption; Frequency; Logic design; Process design; Robustness; Voltage; Adders; arithmetic logic unit; high-speed design; low power; multipliers; process variation tolerant design; supply voltage scaling;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2022531
