DocumentCode
1505965
Title
Floating-point behavioral synthesis
Author
Baidas, Zaher ; Brown, Andrew D. ; Williams, Alan Christopher
Author_Institution
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Volume
20
Issue
7
fYear
2001
fDate
7/1/2001 12:00:00 AM
Firstpage
828
Lastpage
839
Abstract
Traditionally, the data processed by a synthesized digital design is fixed (occasionally variable) width integer, and the functional units available are concomitantly simple ladders, subtractors, multipliers, multiplexers, and so on). The aims of paper work are two-fold: 1) to provide a library of high-level floating-point functions (trigonometric, transcendental, complex) to support the synthesis of behavioral designs incorporating complicated sets of floating-point operations and 2) to incorporate this into an optimizing behavioral synthesis environment. Floating-point units are large and cumbersome and an optimization technique that allows the internal substructures of these units to be shared (in both space and time) produces a dramatic decrease in the overall hardware resources required to support a design. The floating-point modules themselves are each implemented in several ways: as an iterative series, by table lookup, and using the coordinate rotation digital computer algorithm. The choice of implementation is left to the optimizer, which makes individual binding choices based on global knowledge of the overall design. This paper describes the library and the optimization algorithm and demonstrates the overall system use with an exemplar: a floating-point quadratic equation solver capable of delivering complex roots, realized using 30% of a Xilinx 40125XV field-programmable gate array
Keywords
circuit optimisation; field programmable gate arrays; floating point arithmetic; high level synthesis; table lookup; coordinate rotation digital computer algorithm; field-programmable gate array; floating-point behavioral synthesis; floating-point modules; high-level floating-point functions; internal substructures; iterative series; optimization technique; overall hardware resources; quadratic equation solver; synthesized digital design; table lookup; Application specific integrated circuits; Computer science; Control system synthesis; Delay; Design optimization; Field programmable gate arrays; Hardware; Integrated circuit synthesis; Iterative algorithms; Software libraries;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.931000
Filename
931000
Link To Document