Title :
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
Author :
Restle, Phillip J. ; Ruehli, Albert E. ; Walker, Steven G. ; Papadopoulos, George
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
7/1/2001 12:00:00 AM
Abstract :
With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simultaneously. In this paper, we show that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems. Applying this method to several examples leads to helpful insights for realistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are critical for the design of critical on-chip interconnects
Keywords :
VLSI; circuit simulation; equivalent circuits; inductance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; time-domain analysis; wiring; capacitive currents; clock distributions; full-wave PEEC time-domain method; full-wave partial element equivalent circuit method; inductance effects; inductive coupling; inductive currents; on-chip interconnect modelling; very large scale integration; wiring problems; Clocks; Delay; Equivalent circuits; Geometry; Inductance; Integrated circuit interconnections; Lead; Time domain analysis; Very large scale integration; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on