Title :
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Author :
Tian, Ruiqi ; Wong, D.F. ; Boone, Robert
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fDate :
7/1/2001 12:00:00 AM
Abstract :
Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography is highly related to local pattern density in the layout. To change local pattern density and, thus, ensure post-CMP planarization, dummy features are placed in the layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization by Stine et al. (1997), Ouma et al. (1998), and Yu et al. (1999), a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations. Two experiments conducted with real design layouts gave excellent results by reducing simulated post-CMP topography variation from 767 Å to 152 Å in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The simulation result from single-layer formulation compares very favorably both to the rule-based approach widely used in industry and to the algorithm by Kahng et al (1999). The multiple-layer formulation has no previously published work
Keywords :
VLSI; chemical mechanical polishing; design for manufacture; integrated circuit layout; integrated circuit manufacture; linear programming; semiconductor process modelling; 152 to 767 angstrom; VLSI manufacturing; cumulative effect; deep-submicrometer VLSI; design layouts; fixed-dissection regime; global density assignment; local insertion; local pattern density; long range oxide planarization; model-based dummy feature placement; multiple-layer considerations; oxide chemical-mechanical polishing manufacturability; post-CMP oxide topography; rule-based approach; single-layer considerations; two-step procedure; Chemicals; Linear programming; Manufacturing industries; Manufacturing processes; Planarization; Robustness; Semiconductor device modeling; Surfaces; Very large scale integration; Virtual manufacturing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on