DocumentCode :
1506196
Title :
A 20 GS/s 1.2 V 0.13 
CMOS Switched Cascode Track-and-Hold Amplifier
Author :
Orser, Heather ; Gopinath, Anand
Author_Institution :
Medtronic Inc., Minneapolis, MN, USA
Volume :
57
Issue :
7
fYear :
2010
fDate :
7/1/2010 12:00:00 AM
Firstpage :
512
Lastpage :
516
Abstract :
A low voltage, low power, high sampling rate track-and-hold amplifier (THA) architecture is proposed. The THA samples at 20 GS/s and combines a distributed amplifier and a switched cascode stage. Power consumption for the circuit is 71 mW and it occupies 0.09 mm2 in 0.13 μm CMOS. The THA delivers up to 34 dB spur-free dynamic range (SFDR) and -32 dB total harmonic distortion (THD) at a supply voltage of 1.2 V. Input return loss remains below -10 dB over all frequencies of interest, while output return loss remains below -15 dB.
Keywords :
CMOS analogue integrated circuits; amplifiers; harmonic distortion; sample and hold circuits; CMOS switched cascode track-and-hold amplifier; THD; high sampling rate track-and-hold amplifier architecture; power 71 mW; size 0.13 mum; spur-free dynamic range; total harmonic distortion; voltage 1.2 V; High-speed integrated circuits; sample-and-hold amplifiers (SHAs); sampled data circuits; track-and-hold amplifiers (THAs);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2010.2048484
Filename :
5475210
Link To Document :
