DocumentCode :
1506219
Title :
Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures
Author :
Fridman, José ; Manolakos, Elias S.
Author_Institution :
Analog Devices Inc., Norwood, MA, USA
Volume :
45
Issue :
5
fYear :
1997
fDate :
5/1/1997 12:00:00 AM
Firstpage :
1291
Lastpage :
1308
Abstract :
We perform a thorough data dependence and localization analysis for the discrete wavelet transform algorithm and then use it to synthesize distributed memory and control architectures for its parallel computation. The discrete wavelet transform (DWT) is characterized by a nonuniform data dependence structure owing to the decimation operation it is neither a uniform recurrence equation (URE) nor an affine recurrence equation (ARE) and consequently cannot be transformed directly using linear space-time mapping methods into efficient array architectures. Our approach is to apply first appropriate nonlinear transformations operating on the algorithm´s index space, leading to a new DWT formulation on which application of linear space-time mapping can become effective. The first transformation of the algorithm achieves regularization of interoctave dependencies but alone does not lead to efficient array solutions after the mapping due to limitations associated with transforming the three-dimensional (3-D) algorithm onto one-dimensional (1-D) arrays, which is also known as multiprojection. The second transformation is introduced to remove the need for multiprojection by formulating the regularized DWT algorithm in a two-dimensional (2-D) index space. Using this DWT formulation, we have synthesized two VLSI-amenable linear arrays of LPEs computing a 6-octave DWT decomposition with latencies of M and 2M-1, respectively, where L is the wavelet filter length, and M is the number of samples in the data sequence. The arrays are modular, regular, use simple control, and can be easily extended to larger L and J. The latency of both arrays is independent of the highest octave J, and the efficiency is nearly 100% for any M with one design achieving the lowest possible latency of M
Keywords :
VLSI; data analysis; digital signal processing chips; distributed memory systems; parallel algorithms; parallel architectures; wavelet transforms; 2-D index space; DWT; VLSI linear arrays; data dependence analysis; data sequence; decimation operation; discrete wavelet transform algorithm; distributed control array architecture; distributed memory architecture; linear space-time mapping; modular arrays; multiprojection; nonlinear transformations; nonuniform data dependence structure; one-dimensional arrays; parallel algorithms; parallel computation; regular arrays; regularized DWT algorithm; samples; three-dimensional algorithm; wavelet filter length; Algorithm design and analysis; Computer architecture; Data analysis; Delay; Difference equations; Discrete wavelet transforms; Distributed control; Nonlinear equations; Performance analysis; Wavelet analysis;
fLanguage :
English
Journal_Title :
Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1053-587X
Type :
jour
DOI :
10.1109/78.575701
Filename :
575701
Link To Document :
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