Title :
A novel low-power full-search block-matching motion-estimation design for H.263+
Author :
Shen, Jun-Fu ; Wang, Tu-Chih ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
7/1/2001 12:00:00 AM
Abstract :
In this paper, a low-power full-search block matching (FSBM) motion-estimation design for the ITU-T recommendation H.263+ standard is proposed. New motion-estimation modes in H.263+ can be fully supported by our architecture. Unlike most previously presented motion-estimation chips, this design can deal with 8×8 and 16×16 block size with different searching ranges. Basically, the proposed architecture is composed of an integer pixel unit with 64 processing elements, and a half-pixel unit with interpolation, a control unit, and data registers. In order to minimize power consumption, gated-clock and dual-supply voltages are used. This design has been realized by TSMC 0.6 μm SPTM CMOS technology. The power consumption is 423.8 mW at 60 MHz and the throughput is 36 fps in CIF format
Keywords :
CMOS digital integrated circuits; code standards; digital signal processing chips; integrated circuit layout; motion estimation; search problems; video codecs; 0.6 micron; 423.8 mW; 60 MHz; CIF format; FSBM motion-estimation design; ITU-T recommendation H.263+ standard; SPTM CMOS technology; architecture; block size; control unit; data registers; dual-supply voltages; gated-clock; half-pixel unit; integer pixel unit; interpolation; low-power full-search block-matching motion-estimation design; power consumption; searching ranges; throughput; Bandwidth; CMOS technology; Clustering algorithms; Energy consumption; Interpolation; Motion estimation; Registers; Throughput; Video coding; Voltage;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
