9.9-mA 5–6 GHz CMOS sub-harmonic direct-conversion receiver using deep n-well BJT

Author

Wei-Ling Chang ; Chin-Chun Meng ; Jin-Siang Syu ; Chia-Ling Wang ; Guo-Wei Huang

Author_Institution

Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

19-23 Jan. 2014

Firstpage

47

Lastpage

49

Abstract

A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.

Keywords

CMOS analogue integrated circuits; bipolar transistors; field effect MMIC; flicker noise; low-power electronics; microwave receivers; voltage control; CMOS sub-harmonic direct conversion receiver; IF stage; RF stage; current 5.5 mA; current 9.9 mA; deep n-well BJT; flicker noise problem; frequency 5 GHz to 6 GHz; low-power sub-harmonic direct-down receiver; mixer switching core; size 0.18 mum; subsequent IF VGA; vertical-NPN bipolar junction transistors; voltage 1.8 V; voltage gain controls; wide tuning range; 1f noise; CMOS integrated circuits; Gain; Mixers; Radio frequency; Receivers; Tuning; 8-phase signal generator; Low power; deep n-well vertical-NPN bipolar junction transistor; direct-conversion receiver; low flicker noise; sub-harmonic mixer;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in Rf Systems (SiRF), 2014 IEEE 14th Topical Meeting on

Conference_Location

Newport Beach, CA

Type

conf

DOI

10.1109/SiRF.2014.6828507

Filename

6828507