Title :
FunState-an internal design representation for codesign
Author :
Strehl, Karsten ; Thiele, Lothar ; Gries, Matthias ; Ziegenbein, Dirk ; Ernst, Rolf ; Teich, Jürgen
Author_Institution :
ETAS GmbH, Stuttgart, Germany
Abstract :
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model´s state transitions in the form of a periodic graph. The feasibility of the novel approach is shown with an asynchronous transfer mode switch example.
Keywords :
Petri nets; asynchronous transfer mode; data flow graphs; finite state machines; formal specification; formal verification; functional programming; hardware-software codesign; scheduling; Boolean dataflow; FunState; Petri net; asynchronous transfer mode switch; communicating state machine; computation model; cyclostatic dataflow; formal specification; formal verification; functional programming; hardware-software codesign; internal design model; marked graph; periodic graph; state machine; symbolic scheduling; synchronous dataflow; Communication system control; Computational modeling; Computer networks; Dynamic scheduling; Electronic mail; Functional programming; Hardware; Petri nets; Processor scheduling; Switches;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on